Open Access Journal

ISSN : 2456-1304 (Online)

International Journal of Engineering Research in Electronics and Communication Engineering(IJERECE)

Monthly Journal for Electronics and Communication Engineering

Open Access Journal

International Journal of Science Engineering and Management (IJSEM)

Monthly Journal for Science Engineering and Management

ISSN : 2456-1304 (Online)

Low-Power VLSI Design Strategies and Its Involvement with New Techniques

Author : P. Sayanna 1

Date of Publication :23rd November 2016

Abstract: The significant goal of this approach is to outline another circuit with low-control utilization, which is more productive and clever for offering help to most recent innovations and developments, for example, compact handsets, cell phones, callingtablets, portable PCs/PCs and some more. In electronic-space, low-control wordings are most astounding needs, control exhaustment is a standout amongst the most essential focus in measuring up to with speed-and-execution' of VLSI chips. The significant difficulties' available into the planning of low-control VLSI chips resemble: size and similarity and power go down. Another real issue emerge while outlining the circuit of low-control VLSI configuration is budgetary viewpoint, that is taken a toll savvy reducements are required to make such gadgets. For control upkeep plot, spillage/spillage current in like manner accepts a basic part in low power VLSI designs. Spillage/spillage current is transforming into an obviously indispensable piece of the total power dissipating of facilitated circuits. This framework depicts about the diverse systems, approaches and in addition control organization plans for low power circuits and structures. For all the whole arrangement of low-control outlining of VLSI chips ensures that the cos lessening and versatility of gadget with appropriate power administration plans. Future troubles that must be met to plots low power predominant circuits are similarly discussed.

Reference :

    1. Michael Keating, David Flynn, Robert Aitken, Ala Gibsons and Kaijian Shi, “Low Power Methodology Manual for System on Chip Design”, Springer Publications, New York, 2007.
    2. Creating Low-Power Digital Integrated Circuits The Implementation Phase, Cadence, 2007.
    3. Liu, Weidong, Xiaodong Jin, Xuemei Xi, James Chen, Min-Chie Jeng, Zhihong Liu, Yuhua Cheng, Kai Chen, Mansun Chan, Kelvin Hui, Jianhui Huang, Robert Tu, Ping K Ko, and Chenming Hu, BSIM3v3.3 MOSFET Model User's Manual, Department of Electrical Engineering and Computer Sciences, University of California-Berkeley, 2005.
    4. Glasser, Lance A, and Daniel W Dobberpuhl, TheDesign and Analysis of VLSI Circuits, AddisonWesley Publishing Co, 1985.
    5. Shekar Borkar, "Design Challenges of Technology Scaling," IEEE Micro, July/August 1999, pg 23.
    6.  T. Inukai, et.al, “Boosted Gate MOS (BGMOS): Device/Circuit Cooperation Scheme to Achieve LeakageFree Giga- Scale Integration,” Proc. CICC 2000, pp.409- 412.
    7. F.Hamzaoglu and M. Stan, “Circuit-Level Techniques to Control Gate Leakage for sub 100nm CMOS,” Proc. ISLPED, pp. 60-63, Aug. 2002.
    8. Y. Yeo, et.al, “Direct Tunneling Gate Leakage Current in Transistors with Ultrathin Silicon Nitride Gate Dielectric,” IEEE Electron Devices Letters, vol.21, no.11, pp. 540-542, Nov.2000.

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