Author : Rachana M.K 1
Date of Publication :19th June 2019
Abstract: Advances in miniaturization technologies have had dramatic impacts on our lives. Radios, computers, and telephones that once occupied large volumes now fit in the palm of a hand. Consequently, it is imperative that the underlying electronic hardware perform correctly and be defect free. However, testing and screening electronic components to requisite “zero defect†standards is extremely challenging. This is due to the defectivity and manufacturing variability inherent in aggressively scaled nanometer IC technologies, and the staggering design complexities. At present, systems –on chips (SOCs) incur 10-15% overheads for design-for-test (DFT) circuitry. Even so, defective parts frequently escape the testing process and cause unacceptable failure in operation. Developing improved test methodologies is a continuing and critical challenge for the microelectronics Industry. This paper compares different testing methodologies and their impact on the complex vlsi circuit is analyzed
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