Open Access Journal

ISSN : 2456-1304 (Online)

International Journal of Engineering Research in Electronics and Communication Engineering(IJERECE)

Monthly Journal for Electronics and Communication Engineering

Open Access Journal

International Journal of Science Engineering and Management (IJSEM)

Monthly Journal for Science Engineering and Management

ISSN : 2456-1304 (Online)

A Study on High Performance and Low Power Sram Memories

Author : Suvitha P S 1 Rachana M k 2 Sindhu T V 3 Anigha Johnson 4

Date of Publication :12th June 2019

Abstract: Present day mobile communication devices equipped with large capacity memories in order to fulfill all the multimedia needs of customers. Now a days, design engineer mainly concentrating not only to equip high capacity memories, but also high bandwidth and low power consuming memories. Main advantages of semiconductor memory is that in a very small area it sac store very large data. The SRAM memories are preferred over DRAM because its operation speed is high and large noise margin.In this paper, literature survey on features of various SRAM memory designs was reported

Reference :

    1.  G.Rajesh kumar, k Babulu“Design and performance analysis of low power SRAM using Modified MTMOS,”ARPN journal of engineering and applied sciences, vol. 13, no.4,july 2018
    2. Al-Mutairi H.K. and Ahmad I. 2015. A hybrid mapping algorithm for reconfigurable nanoarchitectures. Journal of Engineering Research. 3(1).
    3. J. Abella, X. Vera, and A. Gonzalez, “Penelope: The NBTI-aware processor,” inProc. 40th IEEE/ACM Int. Symp. Microarchitecture, 2007. 4. H. Akkary, R. Rajwar, and S. T. Srinivasan, “Checkpoint processing and recovery: Towards scalable large instruction window processors,” in Proc. Int. Symp. Microarchitecture (MICRO), Dec. 2003, pp.423–434
    4. N. L. Binkertet al., “The M5 simulator: Modeling networked systems,”IEEE Micro, vol. 26, no.
    5. pp. 52– 60, Jul. 2006. 6. P. Bose, J. Shin, and V. Zyuban, “Method for Extending Lifetime Reliability of Digital Logic Devices Through Removal of Aging Mechanisms,” U.S. Patent 7 489 161, Feb. 10, 2009.
    6. A. Cabe, Z. Qi, S. Wooters, T. Blalock, and M. Stan, “Small embeddable NBTI sensors (SENS) for tracking on-chip performance decay,”inProc. Int. Symp. Quality Electron. Design (ISQED), Mar. 2009, pp.1–6.
    7. S. Feng, S. Gupta, and S. Mahlke, “Olay: Combat the signs of aging with introspective reliability management,” inProc. Workshop QualityAware Design (W-QUAD), 2008.
    8. X. Fu, T. Li, and J. Fortes, “NBTI tolerant microarchitecture design in the presence of process variation,” in Proc. Int. Symp. Microarchitecture (MICRO), Nov. 2008, pp. 399–410.

Recent Article