Date of Publication :20th June 2019

Abstract: With the upcoming fourth generation wireless systems and convergence of multiple radio standards into a single terminal, building blocks are needed that can be configured for computing various algorithms used in different standards. Given these trends and requirements, we require a circuit-sharing design for the DAB receiver to integrate the FFT (fast Fourier transform) and IMDCT (inverse modified discrete cosine transform) operations into the same functional circuit. The proposed technique reduces hardware overhead, enhances circuit efficiency and significantly reduces the cost of DAB receivers. This project proposes another alternative design named the circuit-sharing pipeline design (CSPD) using a single processor with a pipeline scheme to combine two functions, FFT and IMDCT, into the same circuit. The proposed method will reduces the required FPGA chip area and cost of DAB receivers. Analyzing the existing relationship among IMDCT, DCT (discrete cosine transform) and FFT, the IMDCT function can be replaced using a FFT function. The arithmetic unit in the FFT processor can be significantly reduced due to employing the pipeline scheme. Consequently, the circuit redundancies in the IMDCT and FFT functions can be easily eliminated to allow exploitation of the decreased chip area. Results of this proposed architecture demonstrate that the design can provide advantages such as low gate count and small memory size in the DAB receiver

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