Author : Mrs. Vani H 1
Date of Publication :22nd November 2021
Abstract: This project presents the pipelined Fast Fourier Transform (FFT) processor power optimization. Pipelined FFT processor consists of several sub-modules like data buffer, shifter, and rotator (butterfly) which has introduced power consumption to the circuit in a hierarchical design. The objectives of this project are, first, to study the power consumption in term of power during the hierarchical condition for different type of pipelined FFT and next, the objective is to review the facility saving after the optimization process, where the planning is flattened without sub-modules. This project focuses on 64-point pipelined FFT radix-8 algorithms. The design process is in Verilog coding and simulation is in ISIM. Total power for before and after the optimization process is compared. However, all pipelined FFT show lower power consumption after the optimization process
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